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Details of 13.1 Software and IP Changes
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When you export your design to SDK, the SDK workspace is no longer set
automatically set.
SDK
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Cygwin no longer required:
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Custom makefiles use Windows style paths
xbash removed
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MicroBlaze v8.10a support
XMDStub support removed
Project Navigator/EDK Integration
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Project Navigator will no longer support xmp as the top-level source.
New messaging to add top-level HDL results in consistent constraint handling.
Embedded IP
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Several Existing core updates
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See individual change logs and datasheets for specifics.
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AXI Enhancements
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AXI BRAM Controller – Microblaze ECC Block RAM support.
AXI Interconnect – Shared Bus Mode.
Partitioned Clock Domains – AXI VDMA, AXI CDMA, AXI DMA.
AXI Ethernet – Full checksum offload.
System Generator for DSP
VHDL Library Support for Black Box Import
This new Black Box feature allows you to import VHDL modules that have predefined
library dependencies. For example, similar but independent sub-modules can now be
compiled into different libraries other than “work”. A detailed example of how to use this
new feature can be found in the online Help topic titled “Black Box VHDL Library
Support”.
Performance Improvements
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Support for fast simulation model for AXI FFT that provides a 42x speedup.
33% improvement in 1st-time initialization of a model.
2-3x improvement in simulation speed.
MATLAB Support
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MATLAB 2010a and 2010b are fully supported.
Beta support is provided for MATLAB 2011a.
MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2010b).
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
www.xilinx.com
27
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